CHANNELCTRL_CLR

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Interpret as CHANNELCTRL_CLR

DCP channel control register

ENABLE_CHANNEL	Setting a bit in this field enables the DMA channel associated with it 1 (CH0): CH0 2 (CH1): CH1 4 (CH2): CH2 8 (CH3): CH3
HIGH_PRIORITY_CHANNEL	Setting a bit in this field causes the corresponding channel to have high-priority arbitration 1 (CH0): CH0 2 (CH1): CH1 4 (CH2): CH2 8 (CH3): CH3
CH0_IRQ_MERGED	Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt

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